A CMOS Image Sensor with 240μV/e Conversion Gain, 200ke Full Well Capacity and 190-1000nm Spectral Response

In this paper, the structure and the performances of a CMOS image sensor with high conversion gain (CG): 240 μV/e, high full well capacity (FWC): 200 ke, wide spectral response: 190-1000 nm and high robustness to ultraviolet (UV) light are described. The developed CMOS image sensor was fabricated by introducing the following key technologies; small capacitance floating diffusion (FD) structure with lateral overflow integration capacitor (LOFIC) for pixel and a thin surface high concentration p layer with steep dopant profile for photodiode. INTRODUCTION A high sensitivity, high dynamic range and a wide spectral response performance for image sensors are required by various fields such as security, scientific imaging and FA. Image sensors specialized in each of above mentioned performance were developed so far. It would be beneficial to image sensor users to develop an image sensor having all of the advanced performances simultaneously. For obtaining a wide spectral sensitivity, several methods have been challenged [1-5]. It has been reported that a thin surface high concentration p layer with steep dopant profile and a thick p-epitaxial layer in the photodiode (PD) is effective to obtain high sensitivity in a wide spectral range, from UV light to near infrared (NIR) light, and robustness to UV light [2-5]. In order to achieve high CG, ways to reduce FD capacitance (CFD) have been reported [6-9]. Reducing the gate overlap capacitance and p-n junction capacitance are effective for reducing CFD [8]. However, for general four transistor CMOS image sensor, CFD reduction leads to a decrease on FWC. The lateral LOFIC technology was developed in order to achieve both high CG and FWC by a linear response under single exposure time [10]. These technologies have been developed independently, and above mentioned all performances have not been achieved simultaneously in a CMOS image sensor. In this paper, we demonstrate a CMOS image sensor with 240μV/e CG, 200ke FWC and 1901000nm Spectral Response. The PD and circuit structures, operation sequence and measurement results of the fabricated CMOS image sensor are described. DESIGN OF FABRICATED CMOS IMAGE SENSOR In order to achieve high sensitivity to UV light, a thin surface high concentration p layer with steep dopant profile was formed in the flattened Si surface. The CMOS image sensor was fabricated on p-epitaxial layer on n-type Si substrate. The thickness of the pepitaxial layer was 20 μm to improve the sensitivity to NIR light. For reducing the CFD, it is critical to reduce the gate overlap capacitance accounting for the highest percentage of CFD in conventional structure [8]. Then in the FD and the drain of the pixel SF, the implantation process of lightly doped drain (LDD) was removed. Therefore, a self-aligned n diffusion was formed with an offset structure as shown in Fig. 1. It leads to the reduction of gate overlap capacitance. The implantation process of channel stop under FD was not carried out. This contributes to the reduction of p-n junction capacitance. Regarding the metal capacitance, since the pixel SF was placed near the FD, the wiring between FD and the pixel SF was short. Furthermore the other wirings near the FD were separated from it and these lead to a reduction of metal capacitance. Consequently, a high CG is to be achieved [8-9]. While reducing FD capacitance improves the CG, the FWC at FD becomes lower. For resolving this tradeoff, we introduced the LOFIC technology. Then, under a low illumination condition, integrated photoelectrons are completely transferred from the PD to the small capacitance FD, and high CG signal is read